NDLI: Design and implementation of a sub-threshold BFSK transmitter

Content Provider	IEEE Xplore Digital Library
Author	Paul, S. Garg, R. Khatri, S.P. Vaidya, S.
Copyright Year	2009
Description	Author affiliation: Intel Corporation, Austin, TX 78746, USA (Paul, S.) \|\| Department of ECE, Texas A&M University, College Station 77843, USA (Garg, R.; Khatri, S.P.) \|\| Lawrence Livermore National Laboratories, CA 94550, USA (Vaidya, S.)
Abstract	Power Consumption in VLSI circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. However, a growing class of applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used for these applications. Unfortunately, sub-threshold circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this paper we implement and test a robust subthreshold design flow which uses circuit level PVT compensation to stabilize circuit performance. We design and fabricate a subthreshold BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps. Experiments using the fabricated die, verify the functionality of the design show that the sub-threshold circuit consumes 19.4× lower power than the traditional standard cell based implementation on the same die.
Starting Page	664
Ending Page	672
File Size	6382895
Page Count	9
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810373
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transmitters Circuit testing Energy consumption Very large scale integration Electronics industry Circuit synthesis Voltage Temperature sensors Robustness Circuit optimization Adaptive Body Biasing Sub-threshold Design Low Power BFSK
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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