NDLI: Incremental power optimization for multiple supply voltage design

Content Provider	IEEE Xplore Digital Library
Author	Yuchun Ma Xiang Qiu Xiangqing He Xianlong Hong
Copyright Year	2009
Description	Author affiliation: Department of Computer Science and Technology, Tsinghua University, Beijing, 100084, China (Yuchun Ma; Xianlong Hong) \|\| Institute of Microelectronics, Tsinghua University, Beijing, 100084, China (Xiang Qiu; Xiangqing He)
Abstract	Multiple supply voltage (MSV) is an effective method to optimize the chip power consumption. In MSV design, the voltage island is a crucial concern that the blocks with the same voltage level are clustered into one or more voltage islands to reduce the costs of voltage supply network and level converter. The distribution of voltage islands depends on not only the feasible voltage assignment based on timing analysis, but also the physical adjacency between blocks. In traditional post-floorplan voltage island generation approaches, the fixed layout of blocks limits the power optimization greatly. Instead of a start-over of searching process to generate better solutions, which suffers from long run time and poor scalability, in this paper, we propose an incremental power optimization methodology to further optimize the power consumption of traditional post-floorplan MSV design without compromising the circuit performance. A net-flow based timing slack distribution algorithm is proposed to obtain maximal power reduction, considering both the characters of each block and the circuit topology. Then we incrementally change the floorplan to re-construct the voltage island distribution based on the physical constraint graph, while the chip area, the total wire length and the performance are considered simultaneously. The experimental results show that our methodology can reduce the power consumption while the chip area, the total wire length and the power supply network cost are maintained at the same time.
Starting Page	280
Ending Page	286
File Size	402720
Page Count	7
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810308
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Design optimization Voltage Energy consumption Costs Timing Power generation Wire Optimization methods Scalability Circuit optimization Voltage island Floorplan MSV
Content Type	Text
Resource Type	Article

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