NDLI: An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process

Content Provider	IEEE Xplore Digital Library
Author	Rajagopal, K. Aatmesh Menezes, V.
Copyright Year	2009
Description	Author affiliation: Texas Instruments India Pvt. Ltd., Bagmane Tech Park Bangalore, Karnataka - 560093 INDIA (Rajagopal, K.; Aatmesh; Menezes, V.)
Abstract	The aggressive scaling of CMOS process is central to the continued performance enhancement of microprocessors. While the process scales every generation the I/O interface standards do not change at the same rate. This introduces a host of reliability issues. One not only needs to design for performance, but should also meet the reliability goals in the scaled technology for these standards. This paper presents a 3.3V I/O buffer designed using 1.8V transistors in a 65nm bulk CMOS process. Proposed I/O uses a novel differential amplifier based pre-driver topology, which has excellent gate-oxide reliability, runs at 200MHz and has comparative area and static power of an equivalent I/O in 65nm 3.3V CMOS process.
Starting Page	103
Ending Page	106
File Size	568447
Page Count	4
File Format	PDF
ISBN	9781424429523
DOI	10.1109/ISQED.2009.4810277
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Topology CMOS process Low voltage CMOS technology Differential amplifiers Capacitors Niobium compounds Titanium compounds Instruments Electronic mail Gate-oxide integrity High voltage (3.3V) design differential amplifier reliability NBTI
Content Type	Text
Resource Type	Article

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