NDLI: Quasi-normally-off GaN gate driver for high slew-rate d-mode GaN-on-Si HEMTs

Content Provider	IEEE Xplore Digital Library
Author	Moench, S. Costa, M. Barner, A. Kallfass, I. Reiner, R. Weiss, B. Waltereit, P. Quay, R. Ambacher, O.
Copyright Year	2015
Description	Author affiliation: Fraunhofer Inst. for Appl. Solid State Phys., Freiburg, Germany (Reiner, R.; Weiss, B.; Waltereit, P.; Quay, R.; Ambacher, O.) \|\| Inst. of Robust Power Semicond. Syst., Univ. of Stuttgart, Stuttgart, Germany (Moench, S.; Costa, M.; Barner, A.; Kallfass, I.)
Abstract	This work presents a quasi-normally-off gallium nitride (GaN) transistor with positive gate threshold voltage based on depletion-mode technology, suitable for gate drivers or logic circuits. Quasi-normally-off behaviour is achieved by the series connection of multiple Schottky diodes in the source path of an initially normally-on transistor. As opposed to conventional approaches, a novel quasi-normally-off gate driver circuit avoids the static shoot-through current path in the driver final stage and ensures a safe blocking state of a d-mode power switch in case of driver failure with only one negative driver supply voltage. For evaluation a hybrid integrated GaN power module is built, comprising a 2.4 A gate driver and 600 V/ 24 A boost converter switching cell. Measurements of pulsed inductive switching up to 274 V/ 12 A show gate voltage rise and fall times of 5.4 ns and 3.8 ns, boost converter switch node transition times as low as 1.6 ns and 1.2 ns, and maximum slew-rates up to 91 V/ns during turn-on transitions, and up to 177 V/ns during turn-off transitions, respectively.
Starting Page	373
Ending Page	376
File Size	446836
Page Count	4
File Format	PDF
ISBN	9781479962594
ISSN	1943653X
e-ISBN	9781479962617
DOI	10.1109/ISPSD.2015.7123467
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-10
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Gallium nitride Switches Voltage measurement HEMTs MODFETs dc-dc power converters power transistors gallium nitride driver circuits integrated circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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