NDLI: Rounded edge mesa for submicron SOI CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Haond, M. Le Neel, O.
Copyright Year	1990
Description	Author affiliation: CNET, Meylan, France (Haond, M.)
Abstract	Different isolation features have been proposed for silicon on insulator (SOI): LOCOS, mesa, and reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. The rounded edge mesa (REM) presented allows accurate control of the gate dimensions without shorts. A 0.8 mu m DLM CMOS process was run on ZMR (zone-melting recrystallization) SOI films thinned down to 150 nm. After the REM formation, the pad oxide is stripped and a 15 nm gate oxide is grown followed by a 380 nm N+-polysilicon film deposition. A classical gate etch is then applied. The absence of residues as studied by measuring the resistance of 22 mm long 0.8 mu m spaced 0.8 mu m wide interdigitated polysilicon fingers running on mesas. The absence of subthreshold leakage or bumps in the subthreshold slope confirms that this technique prevents the formation of sidewall parasitic channels.
Starting Page	132
Ending Page	133
File Size	116927
Page Count	2
File Format	PDF
ISBN	0879425733
DOI	10.1109/SOSSOI.1990.145746
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS process Etching Anisotropic magnetoresistance Electrical resistance measurement Fingers Histograms MOSFETs Current density Subthreshold current
Content Type	Text
Resource Type	Article

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