NDLI: Noise overshoot at drain current kink in SOI MOSFET

Content Provider	IEEE Xplore Digital Library
Author	Chen, J. Fang, P. Ko, P.K. Hu, C. Solomon, R. Chan, T.-Y. Sodini, C.G.
Copyright Year	1990
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Chen, J.; Fang, P.; Ko, P.K.; Hu, C.)
Abstract	The bias dependence of the drain current noise power of SOI (silicon-on-insulator) MOSFETs was studied, and low frequency noise overshoot at the drain current was observed. The overshoot has a width of about 0.7 V and exhibits a peak noise power which is two orders of magnitude higher than the normal noise level. The SOI devices used in this study were N-channel polysilicon gate MOSFETs on SIMOX (separation by implantation of oxygen) wafers fabricated with conventional submicron CMOS technology. The SOI film thickness, the buried-oxide thickness, and the gate oxide are 100 nm, 300 nm, and 11.5 nm, respectively. A computer-controlled test system was used to conduct the I-V and noise measurement automatically. A model explaining the occurrence of the noise overshoot and the noise peak is proposed.
Starting Page	40
Ending Page	41
File Size	167276
Page Count	2
File Format	PDF
ISBN	0879425733
DOI	10.1109/SOSSOI.1990.145699
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Low-frequency noise Noise level CMOS technology Silicon on insulator technology Power MOSFET Automatic testing System testing Noise measurement Semiconductor device modeling
Content Type	Text
Resource Type	Article

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