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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kinam Kim Joo-Sung Park |
| Copyright Year | 2001 |
| Description | Author affiliation: Memory Device Bus., Samsung Electron. Co., Kyungki, South Korea (Kinam Kim) |
| Abstract | A 1.8 V 650 mm/sup 2/ 4Gb DRAM fabricated with 0.10 /spl mu/m/sup 2/ cell size has been successfully developed using 0.11 /spl mu/m DRAM technology. Well-proven KrF lithography has been extended with various resolution enhancement techniques for 0.11 /spl mu/m DRAM technology. 80 nm array transistor and sub-80 nm memory cell contact, which are the smallest array transistor ever reported, are successfully developed for high functional yield as well as high chip performance. In addition, many novel DRAM technologies are developed and will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node selfaligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal interconnections. |
| Sponsorship | Chinese Inst. Electron. |
| Starting Page | 178 |
| Ending Page | 182 |
| File Size | 397402 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780365208 |
| DOI | 10.1109/ICSICT.2001.981451 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-10-22 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Random access memory Cleaning Chemical technology Contact resistance Threshold voltage Annealing Silicon compounds Hydrogen Polymers Scalability |
| Content Type | Text |
| Resource Type | Article |
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