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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Xu Qiuxia Qian He Yin Huaxiang Jia Lin Ji Honghao Chen Baoqin Zhu Yajiang Liu Min |
| Copyright Year | 2001 |
| Description | Author affiliation: Microelectron. R&D Center, Acad. Sinica, Beijing, China (Xu Qiuxia) |
| Abstract | The fabrication of the high performance 70 nm CMOS device has been successfully explored. Some innovation technologies such as 3 nm nitrided gate oxide, dual poly-Si gate electrode, lateral local super-steep retrograde channel doping using heavy ion implantation, Ge PAI plus LEI forming 40 nm ultra-shallow S/D extension, thin and low resistance Ti-salicide and Co/Ti-salicide etc. are investigated. By these innovations in technologies, high performance 70 nm CMOS devices with excellent SCE and good driving ability have been fabricated successfully. The 57 stage unloaded 100 nm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V respectively are achieved. |
| Sponsorship | Chinese Inst. Electron. |
| Starting Page | 68 |
| Ending Page | 73 |
| File Size | 349749 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780365208 |
| DOI | 10.1109/ICSICT.2001.981426 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-10-22 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | CMOS technology Fabrication Doping profiles Electrodes Threshold voltage CMOS process Technological innovation Ion implantation Circuit optimization Maintenance |
| Content Type | Text |
| Resource Type | Article |
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