NDLI: SOI and device scaling

Content Provider	IEEE Xplore Digital Library
Author	Hu, C.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Hu, C.)
Abstract	In the past five years, impressive progress has been made in SOI materials, device and process demonstrations, and product research, yet SOI IC technology remains a promise more than a reality. An important reason is that the rate of bulk technology scaling, in terms of gate length, gate oxide thickness, threshold voltage (V/sub t/), and performance has exceeded earlier expectations (Hu, 1995). In an environment of rapidly advancing bulk technology, it was difficult to overcome the concern over the known and unknown risks of adopting SOI technology, as it was not known how the situation might change with future scaling. This paper attempts to highlight some considerations in three phases of device scaling-when bulk device scaling may proceed rapidly, slowly, and with extreme difficulty.
Sponsorship	IEEE Electron Devices Soc
Starting Page	1
Ending Page	4
File Size	367074
Page Count	4
File Format	PDF
ISBN	0780345002
ISSN	1078621X
DOI	10.1109/SOI.1998.723043
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Investments Capacitance MOSFETs Voltage Design optimization Circuit synthesis Costs Integrated circuit interconnections Degradation Circuit optimization
Content Type	Text
Resource Type	Article

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Nanometer Device Scaling in Subthreshold Circuits

Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Scaling tradeoffs for CMOS-based VLSI packaging

Comparison of different extraction methods of small-signal parameters for SOI MOSFETs.

Some design trade-offs for large CNN chips using small-size transistors

Architecture and performance of 3-dimensional SOI circuits

BiCMOS device modeling for RF IC design

New high voltage integrated circuits using self-shielding technique

Fanout-tree restructuring algorithm for post-placement timing optimization

SOI and device scaling

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Nanometer Device Scaling in Subthreshold Circuits

Double-gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM

Scaling tradeoffs for CMOS-based VLSI packaging

Comparison of different extraction methods of small-signal parameters for SOI MOSFETs.

Some design trade-offs for large CNN chips using small-size transistors

Architecture and performance of 3-dimensional SOI circuits

BiCMOS device modeling for RF IC design

New high voltage integrated circuits using self-shielding technique

Fanout-tree restructuring algorithm for post-placement timing optimization

SOI and device scaling