NDLI: Negative bias instability in silicon-on-sapphire n-channel MOSFETs

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Negative bias instability in silicon-on-sapphire n-channel MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Do, N.T. Vu, T.Q. Warren, G. Li, G.P. Tsai, C.S.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA (Do, N.T.)
Abstract	Summary form only given. This paper reports detailed measurements of device degradation in silicon-on-sapphire (SOS) multi-edge n-channel MOSFETs (NMOS) caused by a negative bias-temperature (NET) stress on the gate. The stressed NMOS devices exhibit a negative shift in the threshold voltage, V/sub th/, and an increase in leakage current, I/sub lk/. In contrast, edgeless NMOS devices show no significant changes in their voltage and current characteristics. It is therefore believed that the degradation in the multi-edge NMOS devices is caused by a threshold voltage shift in the edge transistor.
Sponsorship	IEEE Electron Devices Soc
Starting Page	85
Ending Page	86
File Size	187133
Page Count	2
File Format	PDF
ISBN	0780345002
ISSN	1078621X
DOI	10.1109/SOI.1998.723123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Degradation MOS devices Threshold voltage Temperature Stress measurement Subthreshold current Substrates Silicon Pollution measurement
Content Type	Text
Resource Type	Article

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