NDLI: Physical modeling of beneficial dynamic floating-body effects in non-fully depleted SOI CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Dongwook Suh Fossum, J.G.
Copyright Year	1994
Description	Author affiliation: Florida Univ., Gainesville, FL, USA (Dongwook Suh; Fossum, J.G.)
Abstract	The floating-body configuration is desirable in scaled SOI CMOS technology because of area efficacy. Unfortunately it portends various problems, one of which is the premature parasitic-BJT breakdown that occurs in both fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs. In the NFD device, other floating-body effects, some of which can be beneficial, are apparent at drain-source voltages below the breakdown because of the sensitivity of threshold voltage to the body-source bias. This bias, which can be forward or reverse in dynamic operation of the MOSFET, is due to positive or negative excess majority-carrier densities in the floating body. In this paper, we present a physical model for the NFD/SOI MOSFET and use it in a circuit simulator (SOISPICE) to identify and assess beneficial floating-body effects in dynamic operation of scaled CMOS digital circuits.
Starting Page	67
Ending Page	68
File Size	190892
Page Count	2
File Format	PDF
ISBN	0780324064
DOI	10.1109/SOI.1994.514238
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-10-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device modeling MOSFETs Circuit simulation Electron devices Inverters CMOS technology Breakdown voltage Threshold voltage Electric breakdown
Content Type	Text
Resource Type	Article

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