NDLI: High performance bulk MOSFET fabricated on SOI substrate for ESD protection and circuit applications

Content Provider	IEEE Xplore Digital Library
Author	Mansun Chan King, J.C. Ko, P.K. Chenming Hu
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Mansun Chan; King, J.C.; Ko, P.K.; Chenming Hu)
Abstract	With the rapid advancement of SOI technology, SOI device and circuit performances keep steadily improving. However, some fundamental problems such as self-heating and ESD are still un-resolved. Such adverse effects can be easily dealt with by combining bulk technologies with current SOI technologies on the same wafer. It has been shown that NMOS buffers built on the substrate of SOI wafers can provide significant improvement in ESD protection for SOI circuits. Also, the availability both SOI and bulk technologies can facilitate the design of high performance circuits. Integration of SOI and bulk technologies can easily be done after selectively etching of the silicon film and buried oxide. However, due to the difference in surface quality, the performance of these substrate MOSFETs is not very clear. Issues such as electron mobility, gate oxide quality and hot carrier reliability have to be addressed. In this paper, the performance of substrate MOSFETs fabricated on SIMOX wafers are evaluated and compared with normal bulk wafers fabricated in the same process lot.
Starting Page	61
Ending Page	62
File Size	186698
Page Count	2
File Format	PDF
ISBN	0780324064
DOI	10.1109/SOI.1994.514235
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-10-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFET circuits Electrostatic discharge Substrates MOS devices Protection Availability Etching Silicon Semiconductor films Electron mobility
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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