NDLI: Low energy process variation tolerant digital image processing system design based on accuracy-energy tradeoffs

Content Provider	IEEE Xplore Digital Library
Author	Se Hun Kim Mukhopadhyay, S. Honggab Kim Wolf, M.
Copyright Year	2011
Description	Author affiliation: School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA (Se Hun Kim; Mukhopadhyay, S.; Honggab Kim; Wolf, M.)
Abstract	In this paper, we present a low energy image processing system design based on efficient accuracy-energy tradeoffs. The proposed design allows aggressive voltage scaling in the presence of process variation by employing an error concealing method based on the inherent error tolerance of digital signal processing applications. Based on a system-level analysis, we demonstrate that significant energy savings can be achieved from voltage scaling and switching activity reduction for computational components. Using the proposed method, we can also achieve energy savings for other subsystems such as memory by increasing compression ratio. The experimental results show that average overall energy savings of up to ∼50% are possible over a conventional design in a 45nm technology.
Starting Page	106
Ending Page	111
File Size	648280
Page Count	6
File Format	PDF
ISBN	9781457719202
ISSN	21623562
e-ISBN	9781457719219
DOI	10.1109/SiPS.2011.6088958
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-04
Publisher Place	Lebanon
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Delay Image coding Energy consumption Computer architecture Image quality Degradation process variation Low power design aggressive voltage scaling image compression
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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