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Process variation tolerant low power dct architecture.
| Content Provider | CiteSeerX |
|---|---|
| Author | Banerjee, Nilanjan Roy, Kaushik Karakonstantis, Georgios |
| Abstract | Abstract: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain “good ” image quality with Peak Signal to Noise Ratio(PSNR)> 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology. 1. |
| File Format | |
| Access Restriction | Open |
| Subject Keyword | Contributive Towards Psnr Improvement Long Path Digital Image Intermediate Computation Architecture Design Considerable Power Saving Dct System Peak Signal Image Quality Psnr Improvement Good Image Quality Impose Contradictory Requirement Large Improvement Video Compression 2-d Discrete Cosine Transform Signal Path Large Process Variation Nm Process Technology Noise Ratio Process Parameter Variation Gradual Degradation Aggressive Voltage Small Psnr Degradation Dct Architecture Power Dissipation Possible Delay Error Low Power Operation Process Parameter Aggressive Voltage Scaling Novel Dct Architecture Scaled Supply Voltage Supply Voltage Scaling |
| Content Type | Text |
| Resource Type | Article |
