NDLI: Embedded transition inversion coding for low power serial link

Content Provider	IEEE Xplore Digital Library
Author	Wen-Chih Huang Chih-Hsing Lin Ching-Te Chiu
Copyright Year	2011
Description	Author affiliation: Department of Computer Science National Tsing Hua University, Hsin-Chu, Taiwan (Wen-Chih Huang; Ching-Te Chiu) \|\| Institute of Communications Engineering, National Tsing Hua University, Taiwan (Chih-Hsing Lin)
Abstract	Serial link interconnection has generated a lot of attention in on-chip bus design due to its advantages over multibit parallel interconnection in terms of crosstalk, skew, and area cost. However, serializing a multi-bit parallel bus tends to increase the bit transition and power dissipation. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to address the problem of the extra indication bit. This ETI coding scheme reduces the transition by up to 31% compared with the encoding followed by serial (ES) scheme. The analysis and simulation results, in this study indicate that the proposed coding scheme produces a low bit transition for different kinds of data pattern.
Starting Page	102
Ending Page	105
File Size	455071
Page Count	4
File Format	PDF
ISBN	9781457719202
ISSN	21623562
e-ISBN	9781457719219
DOI	10.1109/SiPS.2011.6088957
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-04
Publisher Place	Lebanon
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Clocks Simulation System-on-a-chip Delay Detectors Mobile communication
Content Type	Text
Resource Type	Article

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