NDLI: Hardware efficiency versus error probability in unreliable computation

Content Provider	IEEE Xplore Digital Library
Author	Yangyang Tang Boutillon, E. Jego, C. Jezequel, M.
Copyright Year	2011
Description	Author affiliation: Université de Bretagne Sud, UMR CNRS 3192 Lab-STICC, Lorient, France (Yangyang Tang; Boutillon, E.) \|\| Institut Polytechnique Bordeaux, UMR CNRS 5218 Lab-IMS, Bordeaux, France (Jego, C.) \|\| Institut TELECOM/TELECOM Bretagne, UMR CNRS 3192 Lab-STICC, Brest, France (Jezequel, M.)
Abstract	For the purpose of mitigating the effect of transient error in unreliable architecture, many authors have proposed redundant computation (sensitive to error) and an error-free correction unit. In this paper, taking into account that the correction unit is also subject to error, we propose to evaluate the quality of an architecture using not only its efficiency (i.e. the normalized number of operation per area and per unit of time), but also its final output error rate. The new criteria, namely Reliability-Efficiency Criteria (RE-Criteria) thus defines a two dimensional space of solution, i.e. a Pareto distribution [1]. After revisiting well-known correcting techniques with the RE-Criteria, we give an example of Pareto distribution based on a classical FIR filter performed with the error-correcting mechanism based architectures.
Starting Page	168
Ending Page	173
File Size	496954
Page Count	6
File Format	PDF
ISBN	9781457719202
ISSN	21623562
e-ISBN	9781457719219
DOI	10.1109/SiPS.2011.6088969
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-04
Publisher Place	Lebanon
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Finite impulse response filter Error probability Decoding Reliability Clocks Computer architecture RNS Hardware Efficiency Error Probability Reliable Computation FIR Filter
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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