NDLI: High Surface Planarity Die Bonding of Large Optical Chips

Content Provider	IEEE Xplore Digital Library
Author	Kunzelmann, U. Wagner, M. Schenk, H. Lakner, H.
Copyright Year	2005
Description	Author affiliation: Fraunhofer Institute for Photonic Microsystems (IPMS), Maria-Reiche-Str. 2, 01109 Dresden, Germany, www.ipms.fraunhofer.de, Phone +49 351 8823-209, Fax +49 351 8823-266, e-mail kuenzelm@ipms.fraunhofer.de (Kunzelmann, U.)
Abstract	Analog Spatial Light Modulators (ASLM) are highly specialised MOEMS devices, which, in our case, are used as programmable mask in extremely high-resolution DUV mask writing systems. Resolution, precision, contrast and optical uniformity of the mask patterns produced by this new type of mask writers depend on the local and global planarity as well as on the optical contrast of the ASLM devices [1]. Definition, measurement and calculation of the global flatness (GF) of the active area of one-mega pixel ASLM devices, developed and fabricated at the Fraunhofer IPMS in Dresden, is described and applied for the investigations of parameters influencing the chip planarity. Parameters of an adhesive chip bonding technique have been varied and optimised with respect to improved GF. In particular, the influence of the die bonding layers printed on the die attach was investigated. Additionally, an approach based on ultraprecision micro-milling of a sacrificial layer deposited on the die attaches to improve its planarity and thus the GF of the die-bonded chip has been successfully performed.
Starting Page	117
Ending Page	122
File Size	6303033
Page Count	6
File Format	PDF
ISBN	0780395530
DOI	10.1109/POLYTR.2005.1596499
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-10-23
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microassembly Optical modulation Optical devices Modulation coding Ultraviolet sources Writing Spatial resolution Area measurement Semiconductor device measurement Bonding Chip Planarity Micro-Optical-Mechanical Systems (MOEMS) Advanced Chip Bonding Global Flatness
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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