NDLI: Analysis of MOS resistive gate transistors for application in analog multipliers

Content Provider	IEEE Xplore Digital Library
Author	du Plessis, M. Schieke, P.
Copyright Year	1998
Description	Author affiliation: Carl & Emily Fuchs Inst. for Microelectron., Pretoria Univ., South Africa (du Plessis, M.)
Abstract	Placing two contacts on the gate electrode of a MOS transistor allows one to establish a lateral electric field in the resistive gate. The electric field in the gate electrode modifies the inversion charge density and potential profile in the channel of the device, thus modulating the drain current. It was found that a transistor with two gate contacts (one near the source and the other near the drain) above a rectangular active channel region, combined with a narrowing of the gate electrode width going from source to drain, can be used as a multiplying device. This device was simulated and it is shown that a single transistor can be used as a square-law device. Placing two transistors in parallel leads to four quadrant analog multiplication. The square-law and multiplier circuits have a differential input dynamic range of several volts. Device simulation results show that resistive gate devices with nonrectangular gate geometries can be used in novel analog multiplier applications.
Starting Page	224
Ending Page	227
File Size	386387
Page Count	4
File Format	PDF
ISBN	0780345134
DOI	10.1109/COMMAD.1998.791626
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-14
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Electrodes Geometry Circuit simulation Immune system Resistors Semiconductor device modeling Threshold voltage Microelectronics Africa
Content Type	Text
Resource Type	Article

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