NDLI: An Improved Fault Simulation Approach Based on Verilog with Application to ISCAS Benchmark Circuits

Content Provider	IEEE Xplore Digital Library
Author	Das, S.R. Mukherjee, S. Petrm, H.M. Assaf, M.H. Sahinoglu, M. Wen-Ben Jone
Copyright Year	2006
Description	Author affiliation: Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont. (Das, S.R.; Mukherjee, S.; Petrm, H.M.; Assaf, M.H.)
Abstract	This paper presents an approach to fault simulation in the particular context of ISCAS 85 combinational benchmark circuits based on hardware description language (HDL) specification of their gate level netlists. The approach, exploiting the existing force and release features available in Verilog, builds an effective fault simulator by properly utilizing Verilog syntax with application to fault modeling. The implemented simulator system is able to emulate all of the ISCAS 85 combinational circuits. Experimental results show that access to the source code of HDL simulator or its modification is not a requirement to compute faulty responses from a circuit under test (CUT). The proposed simulator is platform independent, thereby making its utility substantially worthwhile
Starting Page	1902
Ending Page	1907
File Size	118407
Page Count	6
File Format	PDF
ISBN	0780393597
ISSN	10915281
DOI	10.1109/IMTC.2006.328308
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-24
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Hardware design languages Circuit testing Computational modeling Benchmark testing Integrated circuit modeling Built-in self-test Test pattern generators Context modeling Verilog hardware description language (HDL) Built-in self-testing (BIST) fault simulation ISCAS benchmark circuits
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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