NDLI: Fault simulation and response compaction in full scan circuits using HOPE

Content Provider	IEEE Xplore Digital Library
Author	Das, S.R. Assaf, M.H. Petriu, E.M. Jone, W.-B.
Copyright Year	2001
Description	Author affiliation: Sch. of Inf. Technol. & Eng., Ottawa Univ., Ont., Canada (Das, S.R.; Assaf, M.H.; Petriu, E.M.)
Abstract	This paper presents results on fault simulation and response compaction on ISCAS 89 full scan sequential benchmark circuits using HOPE-a fault simulator developed for synchronous sequential circuits that employs parallel fault simulation with heuristics to reduce simulation time in the context of design space-efficient support hardware for built-in self-testing of VLSI circuits. The techniques utilized in the paper take advantage of sequence characterization developed previously by the authors for response data compaction in the case of ISCAS 85 combinational benchmark circuits, using ATALANTA, FSIM, and COMPACTEST, under conditions of both stochastic independence and dependence of single and double line errors, and then apply these concepts to the case of full scan sequential benchmark circuits using the fault simulator HOPE.
Sponsorship	IEEE Instrum. Measurement Soc
Starting Page	607
Ending Page	612
File Size	737462
Page Count	6
File Format	PDF
ISBN	0780372182
ISSN	10915281
DOI	10.1109/IMTC.2002.1006911
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Compaction Circuit testing Built-in self-test Computational modeling Context modeling Hardware Test pattern generators Costs
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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