NDLI: Further studies on improved test efficiency in cores-based system-on-chips using ModelSim verification tool

Content Provider	IEEE Xplore Digital Library
Author	Das, S.R. Hossain, A. Li, J.F. Petriu, E.M. Biswas, S.N. Jone, W.B. Assaf, M.H.
Copyright Year	2009
Description	Author affiliation: Dept. of Electr. Eng. Technol., Georgia Southern Univ., Statesboro, GA, USA (Biswas, S.N.) \|\| Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH, USA (Jone, W.B.) \|\| Sch. of Inf. Technol. & Eng., Univ. of Ottawa, Ottawa, ON, Canada (Das, S.R.; Hossain, A.; Li, J.F.; Petriu, E.M.) \|\| Univ. of Trinidad & Tobago, Arima, Trinidad and Tobago (Assaf, M.H.)
Abstract	The complexity of modern digital circuits has increased enormously because of paradigm shift from system-on-board to designs embracing embedded cores-based system-on-chips (SOCs). The ensuing intricacy has resulted in a huge challenge in setting up their appropriate fault analysis and testing environment. Though enormous efforts were directed to rapidly test very large-scale integration(VLSI) circuit chips under reasonable cost constraints, with technological advances, new barriers emerged. The subject paper, augmenting earlier works of authors, pertains to developing method that aims to test verify circuit architecture in a hardware-software co-design environment, specifically targeting embedded SOCs. The concept of design-for-testability (DFT) is utilized in this paper, using ModelSim simulation and verification tool, to test simulate the overall design. In earlier works, simulation experience on ISCAS 85 combinational benchmark circuits was provided. In this study, some partial simulation results on ISCAS 89 full scan sequential benchmark circuits are furnished because of space contraint, along with discussion of proposed algorithm and programming basisin a context of ModelSim.
Sponsorship	IEEE Instrum. Meas. Soc.
Starting Page	1132
Ending Page	1137
File Size	460322
Page Count	6
File Format	PDF
ISBN	9781424433520
ISSN	10915281
DOI	10.1109/IMTC.2009.5168624
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-05
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing System-on-a-chip Circuit testing Circuit simulation Benchmark testing Context modeling Digital circuits Circuit faults Very large scale integration Costs Verilog HDL Built-in self-test (BIST) fault injection fault simulation module under test (MUT) system-on-chips (SOCs) test pattern generator (TPG)
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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