NDLI: A simple but effective ESD robustness improvement for NMOS transistors used in I/O pads

Content Provider	IEEE Xplore Digital Library
Author	Tien, D.K.C. Koo Sang Sool
Copyright Year	2011
Description	Author affiliation: Process Development, XFAB Sarawak Sdn Bhd, 93350 Kuching, Sarawak, Malaysia (Tien, D.K.C.; Koo Sang Sool)
Abstract	This paper presents a simple but effective way to improve an NMOS transistor's ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper. Both TLP (Transmission Line Pulse) measurements and HBM (Human Body Model) ESD tests are performed to assess the weakest area of NMOS regarding ESD robustness. Finally this NMOS ESD robustness is doubled by changing only one mask (without introducing any process or design change). The change offers potential for all NMOS transistors used in the same configuration of ESD protection circuits.
Starting Page	161
Ending Page	166
File Size	865690
Page Count	6
File Format	PDF
ISBN	9781612848440
e-ISBN	9781612848464
DOI	10.1109/RSM.2011.6088315
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-28
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Current measurement Implants Electrostatic discharges Robustness Transistors Junctions MOS devices
Content Type	Text
Resource Type	Article

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