NDLI: Effective parameterization for IP re-use

Content Provider	IEEE Xplore Digital Library
Author	Seng, F.C.K. Manaf, A.B.A. Lim Han Wooi
Copyright Year	2011
Description	Author affiliation: Intel Microelectronics (M) Sdn. Bhd., Bayan Lepas FTZ, Penang, Malaysia (Lim Han Wooi) \|\| School of Electrical & Electronic Engineering, Universiti Sains Malaysia, 14300, Nibong Tebal, Penang, Malaysia (Seng, F.C.K.; Manaf, A.B.A.)
Abstract	The advancement of fabrication technology has doubled the silicon capacity every 18 months. Furthermore, design companies are trying to plug in advance and complex design on a system-on-a-chip (SoC). Yet, the time to implement such a complex design is very long. As a result, this widens the gap between silicon capacity and design productivity. In order to solve the productivity gap problem, this research is introducing a parameterized intellectual property (IP) reuse methodology framework in SoC design. This methodology improves the productivity, design quality and time-to-market of SoC design. The proposed methodology was tested using programmable interval timer (PIT). The results not only show this methodology has successfully reduced the entire IP power consumption and area utilization by 41.74% and 2.42% respectively, but also increase IP's portability, reusability.
Starting Page	139
Ending Page	143
File Size	1281326
Page Count	5
File Format	PDF
ISBN	9781612848440
e-ISBN	9781612848464
DOI	10.1109/RSM.2011.6088310
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-09-28
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Measurement Parameterize IP reuse Radiation detectors SoC Time-to-market Registers Power dissipation IP networks System-on-a-chip Hardware design languages Reconfiguration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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