NDLI: SSTL based green image ALU design on different FPGA

Content Provider	IEEE Xplore Digital Library
Author	Das, T. Pandey, B. Rahman, M.A. Kumar, T.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., South Asian Univ., New Delhi, India (Das, T.; Pandey, B.; Rahman, M.A.; Kumar, T.)
Abstract	In this paper, green Image ALU is designed in Xilinx ISE 14.6 using different IO standard of SSTL in 40 nm Virtex-6 and Spartan-6 FPGA. We are comparing different SSTL IO standard to get reduction in IO power. We accomplish energy efficiency with respect to low voltage impedance, by using SSTL technology. In this entire work, we are using different classes of SSTL and observe that when image ALU operates at 1 THz device operating frequency with SSTL18_I_DCI I/O Standard using virtex-6 FPGA, there is 45.55% decrease in IO power and 20.50% in Clock power as compared to SSTL18_II IO Standard. Similarly when we operate Image ALU at 1 THz using Spartan-6, there is 33.31% reduction in IO power of SSTL18_I with respect to SSTL18_II Standard. There are 16 different arithmetic and logic operations in Image ALU. The Clock power, Logic power and Signal power of Image ALU remains same using Spartan-6 I/O Standard.
Starting Page	146
Ending Page	150
File Size	669001
Page Count	5
File Format	PDF
e-ISBN	9781467361262
DOI	10.1109/ICGCE.2013.6823417
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Efficient Design Power demand FPGA Green Computing Image ALU I/O standard Standards I/Os Power Low voltage Energy efficiency Field programmable gate arrays SSTL Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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