NDLI: Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit

Content Provider	IEEE Xplore Digital Library
Author	Bidhul, C.B. Hampannavar, N. Joseph, S. Jayakrishnan, P. Kumaravel, S.
Copyright Year	2013
Description	Author affiliation: Sch. of Electron. Eng., VIT Univ., Vellore, India (Bidhul, C.B.; Hampannavar, N.; Joseph, S.; Jayakrishnan, P.; Kumaravel, S.)
Abstract	The concept of reconfigurable computing facilitates flexibility of the software along with high performance of hardware. The FPGA based hardware provides bit level or fine grain re-configurability where as ASIC based hardware is capable of course grain reconfiguration that lead to accelerated (hardware) performances with lesser re-programming time. This paper presents the implementation of a multiplication accumulation (MAC) unit which is reconfigurable with respect to word lengths of the operands. The unit is capable of processing signed and unsigned numbers as per the requirement. The sub units- multiplier, adder and sign selection units are reconfigurable, can function as independent units and together as accumulation unit. Reconfiguration with word length, throughput or data type is implemented with the help of a set of multiplexers, de-multiplexers and pipeline registers. Two implementations using different adders were compared. One design uses carry save addition in adder module and the other uses ripple carry addition. The implementation using ripple carry adder shows significant improvement in area and power consumption over the other. However, the use of carry save adder gives about 2% improvement on speed than its counterpart.
Starting Page	225
Ending Page	230
File Size	794842
Page Count	6
File Format	PDF
e-ISBN	9781467361262
DOI	10.1109/ICGCE.2013.6823433
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Ripple Carry Adder Pipelines Carry Save Adder Computer architecture Very large scale integration Hardware Registers Adders MAC Clocks Reconfiguration
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

VLSI implementation of GSC architecture with a new ripple carry adder

Design of high performance 64 bit MAC unit

A very fast and low power carry select adder circuit

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Fast modular multiplication with carry save adder

Modified energy efficient carry save adder

Design of high performance Multiply-Accumulate Computation unit

Performance analysis of different types of adder for high speed 32 bit multiply and accumulate unit.

A Prefix Based Reconfigurable Adder

Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit

Similar Documents

VLSI implementation of GSC architecture with a new ripple carry adder

Design of high performance 64 bit MAC unit

A very fast and low power carry select adder circuit

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Fast modular multiplication with carry save adder

Modified energy efficient carry save adder

Design of high performance Multiply-Accumulate Computation unit

Performance analysis of different types of adder for high speed 32 bit multiply and accumulate unit.

A Prefix Based Reconfigurable Adder

Comparison of architectures of a coarse-grain reconfigurable multiply-accumulate unit