NDLI: Synthesizing power gating sequence in pausible clock based GALS designs

Content Provider	IEEE Xplore Digital Library
Author	Rajakumari, A. Sharma, N.S.M. Kishore, K.L. Petta, V.K.
Copyright Year	2013
Description	Author affiliation: JNTU Ananthapur, Ananthapur, India (Kishore, K.L.) \|\| Synopsys, Inc., Hillsboro, OR, USA (Petta, V.K.) \|\| BVCE Coll., Odalarevu, India (Sharma, N.S.M.) \|\| B.V.R.I.T., Hyderabad, India (Rajakumari, A.) With the improving evolution in VLSI technology most of the digital circuits are becoming SOCs. However most of the SOC systems are synchronous designs and the issues like clock skew, power consumption and EMI are related to clock network. Asynchronous circuits can offer benefits like reduced power and improved performance. However implementing whole design with asynchronous design style is a challenge due to lack of CAD tools. The GALS (Globally-Asynchronous Locally-Synchronous) design methods brings compromise between synchronous and asynchronous design styles by separating each synchronous blocks in SoC with asynchronous interface. Each synchronous block in SoC can perform operation with its own local clock. The data communication among synchronous blocks can be achieved via handshaking signals after pausing the local clocks. Though these GALS system architectures ensures less dynamic power through clock less asynchronous interface the leakage power contribution to total power equation is still a challenge in deep submicron technologies. Power gating is most effective technique for synchronous design to address leakage power. In this paper an asynchronous power gating sequence generation is proposed for GALS synchronous blocks which has to wait long time for data. To corroborate the proposed technique a synthesis flow is proposed to implement asynchronous 8051 micro controller. The implementation was done using Synopsys SAED 90 nm libraries and the experimental results shows 30% leakage power reduction for power gating blocks.
Starting Page	65
Ending Page	70
File Size	488477
Page Count	6
File Format	PDF
e-ISBN	9781467361262
DOI	10.1109/ICGCE.2013.6823401
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	GALS Relative Timing Switches Receivers Synchronization Equations Power Gating Asynchronous Wrappers Petri Nets Clock Gating 4-Phase handshaking Integrated circuit modeling Signal Transition Graph (STG) Clocks
Content Type	Text
Resource Type	Article

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