NDLI: SSTL I/O standard based green communication using Fibonacci generator design on ultra scale FPGA

Content Provider	IEEE Xplore Digital Library
Author	Nagah, S. Kaur, R. Pandey, B. Akbar Hussain, D.M. Kumar, T. Chowdhry, B.S.
Copyright Year	2015
Description	Author affiliation: Dept. of CSE, Indus Univ., Karachi, Pakistan (Kumar, T.) \|\| Dept. of Energy Technol., Aalborg Univ., Aalborg, Denmark (Akbar Hussain, D.M.) \|\| Fac. of EECE, MUET, Pakistan (Chowdhry, B.S.) \|\| Gyancity Res. Lab., New Delhi, India (Nagah, S.; Kaur, R.; Pandey, B.)
Abstract	In this paper six different available classes of Stub-Series Terminated Logic (SSTL) Input/output standard is used for the design of Green Fibonacci generator on 40nm FGPA. That green Fibonacci Generator is used to generate key for Wi-Fi Protected Access in order to make energy efficient communication or green communication possible. Six SSTL I/O standards include SSTL18_I, SSTL18_II, SSTL18_I_DCI (S18ID), SS18IID (S18IID), SSTL15 and SSTL15_DCI. We compared I/O power of SSTL18_I with SSTL18_II, S18ID with S18IID and SSTL15 with SSTL15_DCI on different frequencies ranging from 1GHz-1THz. After comparison it is observed that, SSTL15 is the most energy efficient and S18IIDis the worst energy efficient. Then on comparison of SSTL15 with SSTL18_II_DCI (S18IID), it is found that, when Fibonacci generator is operated at different frequencies like 1GHz, 10GHz, 100GHz and 1THz, the reduction in I/O power requirement of SSTL15 is 77.00%, 45.89%, 19.23% and 14.41% respectively, less than S18IID.
Starting Page	1519
Ending Page	1523
File Size	3729765
Page Count	5
File Format	PDF
ISBN	9789380544151
e-ISBN	9789380544168
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Bharati Vidyapeeth University, New Delhi
Subject Keyword	Fibonacci Generator Generators Energy efficiency Power dissipation Electronic mail I/O standard Standards Field programmable gate arrays I/Os Power SSTL Clocks
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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