NDLI: IO standard based energy efficient ALU design and implementation on 28nm FPGA

Content Provider	IEEE Xplore Digital Library
Author	Pandey, B. Yadav, J. Pattanaik, M.
Copyright Year	2013
Description	Author affiliation: ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India (Pandey, B.; Yadav, J.; Pattanaik, M.)
Abstract	In this work, target design is ALU. To achieve reduction in IOs power we are searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard. There is 85.18% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS12 based ALU design. There is 41.45% power reduction when we migrate from LVCMOS33 based ALU design to LVCMOS25 based ALU design. Target FPGA family is 28nm Artix-7. Verilog is hardware description language used for design of ALU. There is 7.16% reduction in power for only LVCMOS15, when we change drive strength from 16 milliAmpere to 8 milli-Ampere. There is 5.44% reduction in power for LVCMOS18 when we change drive strength from 24 milliAmpere to 8 milli-Ampere. LVCMOS33 is the highest power consumer and LVCMOS12 is the lowest power consumer among the different available LVCMOS IO standard when there is common drive strength applied.
Starting Page	1
Ending Page	5
File Size	1439317
Page Count	5
File Format	PDF
e-ISBN	9781479922758
DOI	10.1109/INDCON.2013.6725996
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-13
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Efficient Power demand Low Power LVCMOS IO standard Logic gates Energy efficiency ALU CMOS integrated circuits 28 nm FPGA Standards Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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