NDLI: Deriving a Methodology for Code Deployment on Multi-Core Platforms via Iterative Manual Optimizations

Content Provider	IEEE Xplore Digital Library
Author	McCool, S. Milligan, P. Sage, P.
Copyright Year	2012
Abstract	In recent years, there has been what can only be described as an explosion in the types of processing devices one can expect to find within a given computer system. These include the multi-core CPU, the General Purpose Graphics Processing Unit (GPGPU) and the Accelerated Processing Unit (APU), to name but a few. The widespread uptake of these systems presents would-be users with at least two problems. Firstly, each device exposes a complex underlying architecture which must be appreciated in order to attain optimal performance. This is coupled with the fact that a single system can support an arbitrary number of such devices. Consequently, fully leveraging the performance capabilities of such a system must come at a cost -- increasingly prolonged development times. Adhering to a methodology will have the significant industrial impact of reducing these development times. This paper describes the continued formulation of such a novel methodology. Two real world scientific programs are optimized for execution on the CUDA platform. Double precision accuracy and optimized speedups (which include PCI-E transfer times) of 15x and 17x are achieved.
Starting Page	1406
Ending Page	1415
File Size	408171
Page Count	10
File Format	PDF
ISBN	9781467309745
DOI	10.1109/IPDPSW.2012.178
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Methodology Racah Registers GPGPU Toolset Graphics processing unit Guidelines Characterization Slater Acceleration Heterogeneous computing Kernel Artificial intelligence
Content Type	Text
Resource Type	Article

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