NDLI: Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier

Content Provider	IEEE Xplore Digital Library
Author	Jaiswal, M.K. Cheung, R.C.C.
Copyright Year	2012
Abstract	Floating point multiplication is a crucial and useful arithmetic operation for many scientific and signal processing applications. High precision requirements of many applications lead to the incorporation of quadruple precision (QP) arithmetics. The logic complexity and performance overhead of quadruple precision arithmetic are quite large. This paper has focused on one of the quadruple precision arithmetic operations, multiplication. We present an efficient implementation of QP multiplication operation on a reconfigurable FPGA platform. The presented design uses much less hardware resource in terms of DSP48 blocks, and slices with a higher performance. Promising results are obtained by comparing the proposed designs with the best reported QP floating point multiplier in the literature. We have achieved more than 50% improvements in the amount of DSP48 block at a slight cost of additional slices, on a Virtex-4 FPGA.
Starting Page	376
Ending Page	382
File Size	347370
Page Count	7
File Format	PDF
ISBN	9781467309745
DOI	10.1109/IPDPSW.2012.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High Performance Computing FPGA Quadruple Precision Floating Point Multiplication Standards Application specific integrated circuits Program processors Signal processing Hardware Reconfigurable Computing Karatsuba Multiplication Field programmable gate arrays Adders Arithmetic
Content Type	Text
Resource Type	Article

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