NDLI: Performance Estimation of GPUs with Cache

Content Provider	IEEE Xplore Digital Library
Author	Parakh, A.K. Balakrishnan, M. Paul, K.
Copyright Year	2012
Abstract	Performance estimation of an application on any processor is becoming a essential task, specially when the processor is used for high performance computing. Our work here presents a model to estimate performance of various applications on a modern GPU. Recently, GPUs are getting popular in the area of high performance computing along with original application domain of graphics. We have chosen FERMI architecture from NVIDIA, as an example of modern GPU. Our work is divided into two basic parts, first we try to estimate computation time and then follow it up with estimation of memory access time. Instructions in the kernel contribute significantly to the computation time. We have developed a model to count the number of instructions in the kernel. We have found our instruction count methodology to give exact count. Memory access time is calculated in three steps, address trace generation, cache simulation and average memory latency per warp. Finally, computation time is combined with memory access time to predict the total execution time. This model has been tested with micro-benchmarks as well as real life kernels like blowfish encryption. matrix multiplication and image smoothing. We have found that our average estimation errors for these applications range from-7.76% to 55%.
Starting Page	2384
Ending Page	2393
File Size	647335
Page Count	10
File Format	PDF
ISBN	9781467309745
DOI	10.1109/IPDPSW.2012.328
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Warp Blocks Address trace Computational modeling FERMI GPU Estimation Memory Prediction Equations Instruction count Graphics processing unit Threads Computer architecture Performance Kernel Clocks Cache
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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