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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chao Wang Xi Li Peng Chen Xiaojing Feng Junneng Zhang Xuehai Zhou |
| Copyright Year | 2012 |
| Abstract | This paper presents a novel data hazards detecting engine, task score boarding, which applies instruction level score boarding algorithm to reconfigurable MPSoC on FPGA for out-of-order task execution. Task score boarding can detect inter-task data dependencies and then assign tasks to different processors or IP cores automatically. When the computing resources are sufficient and no data dependences, task score boarding allows tasks to execute out of order. We implemented the prototype system on a state-of-the-art Virtex5 FPGA board. Experimental results on sample applications demonstrated that the task score boarding can achieve more than 97% of theoretical speedup, which shows it can largely uncover task level parallelism. |
| Starting Page | 282 |
| Ending Page | 287 |
| File Size | 867038 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781467309745 |
| DOI | 10.1109/IPDPSW.2012.33 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-05-21 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Out of order Scoreboarding Parallel processing Task level parallelism Hazards Hardware IP networks Out-of-order execution Field programmable gate arrays Data hazard |
| Content Type | Text |
| Resource Type | Article |
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