NDLI: Energy-Efficient and Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs

Content Provider	IEEE Xplore Digital Library
Author	Yixuan Zhang Morris, R. DiTomaso, D. Kodi, A.
Copyright Year	2012
Abstract	Network-on-Chip (NoC) architecture is considered to be an attractive solution to overcome the combined problems of limited bandwidth and scalability in multicores. Input buffering at the router allows the network to sustain the accepted throughput without performance degradation. However, the input buffers consume a substantial portion of the total power budget, and there have been proposals to reduce the size of these buffers. Eliminating buffers altogether can also reduce the power consumption at low network loads, however at higher loads when conflicts are frequent, deflecting or dropping packets can lead to higher power. In this paper, with both enhancing performance and decreasing power consumption as our goals, we propose a dual-input crossbar design called DXbar, which combines the advantages of buffer less networks to enable low-latency routing at low network load and limited buffering capability to handle excessive packets at high network load. Moreover, we also propose a unified dual-input crossbar that combines the buffer less and buffered approach in one integrated architecture. The dual crossbar network naturally provides fault tolerance and improves the reliability of the network. Dual-input crossbar architecture improves the area overhead, while providing similar performance as dual crossbar architecture. DXbar design not only has superior performance compared to the state-of-the-art designs based on similar motivation, but also achieves significant power savings. The simulation results of the proposed methodology show that DXbar achieves over 15-20% performance improvement and saves at least 15% power over the baseline design for synthetic and Splash-2 benchmarks. We further evaluated the performance by injecting varying percentage of faults into the network for both DOR and WF adaptive routing algorithms. Our results indicate that DOR outperforms WF adaptive routing algorithm at high network loads with increasing percentage of faults.
Starting Page	972
Ending Page	981
File Size	1262687
Page Count	10
File Format	PDF
ISBN	9781467309745
DOI	10.1109/IPDPSW.2012.119
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-05-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Pipelines Computer architecture Switches Network-on-chip Logic gates Routing Crossbar Resource management Fault-Tolerant
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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