NDLI: Delay model for VLSI RLCG global interconnects line

Content Provider	IEEE Xplore Digital Library
Author	Maheshwari, V. Baboo, A. Kumar, B. Kar, R. Mandal, D. Bhattacharjee, A.K.
Copyright Year	2012
Description	Author affiliation: Deptt. of ECE, National Institute of Technology, Durgapur, W.B., India (Kar, R.; Mandal, D.; Bhattacharjee, A.K.) \|\| Deptt. of ECE, School of Engineering and Technology, Apeejay Stya University, Gurgaon, Haryana, India (Maheshwari, V.) \|\| Deptt. of EE, Hindustan College of Science and Technology, Mathura, U.P., India (Baboo, A.) \|\| Deptt. of ECE, F.E.T. Agra College, Agra, U.P., India (Kumar, B.)
Abstract	Due to high packaging density of components, delay modelling is increasingly becoming the bottleneck for the design of high performance VLSI circuits. At higher frequency of operations, of the order of few GHz, the on-chip interconnect is to be analyzed with a distributed RLCG model. Because at very high frequency, the dielectric material deviates from its ideal nature. This gives rise to the shunt conductance matrices. The Elmore delay can deviate for typical RLCG interconnections with ramp input from SPICE computed delay. Since it is independent of rise time of the input ramp signal. In the performance driven synthesis and design of VLSI routing topologies Elmore delay is widely used as an analytical model of interconnect delay. We develop a new analytical delay model based on the first and second moments of the interconnect transfer function when the input is a ramp signal with finite rise time. The simulation results justify the efficacy of the proposed delay estimation model.
Starting Page	201
Ending Page	204
File Size	825663
Page Count	4
File Format	PDF
ISBN	9781467350655
ISSN	21592144
e-ISBN	9781467350679
DOI	10.1109/PrimeAsia.2012.6458654
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Interconnect Analytical models Power transmission lines Computational modeling VLSI Integrated circuit interconnections Very large scale integration System-on-a-chip Distributed RLCG Elmore Delay Ramp Input Delay
Content Type	Text
Resource Type	Article

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