NDLI: Variable input delay CMOS logic for dynamic IR drop reduction

Content Provider	IEEE Xplore Digital Library
Author	Kumar, B.V.P.V. Sharma, N.S.M. Kishore, K.L. Rajakumari, A.
Copyright Year	2012
Description	Author affiliation: BVCE College, Odalarevu, India, 533210 (Sharma, N.S.M.) \|\| JNT University, Ananthapur, Hyderabad, India (Kishore, K.L.) \|\| Synopsys (India) Pvt. Ltd, Hyderabad, India (Kumar, B.V.P.V.) \|\| B.V.R.I.T, Narsapur, Hyderabad, India (Rajakumari, A.)
Abstract	A glitch compensation methodology is proposed in this paper which involves reducing the undesired switching of selected combinational cells from a place and routed standard cell layout in order reduce peak dynamic voltage or IR drop. The proposed methodology can be seamlessly integrated to existing physical design flow. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits when differential delay at the inputs of a gate is greater than inertial delay, which results into notable amount of power consumption. The glitch power is becoming more prominent in lower technology nodes. Introduction of buffers at the input of the Logic gate may reduce glitches, but it results into large area overhead and dynamic power. Hence, the proposed methodology will ensure low dynamic power consumption with less area. The pass transistor logic is used as a compensation circuit and a flow is also proposed for characterizing the pass transistor logic to cater different delay values. The proposed methodology has been validated on a place and routed Multiply Accumulate (MAC) layout implemented using Synopsys SAED 90nm Generic library. Experimental results show 12% to 50% reduction in peak transient IR drop numbers with just 12% reduction in glitch power. Also when compared to standard on-chip decoupling capacitor (Decap) cells insertion method which is used to minimize dynamic IR drop, the proposed method could achieve the same without contributing to extra leakage power.
Starting Page	79
Ending Page	84
File Size	998245
Page Count	6
File Format	PDF
ISBN	9781467350655
ISSN	21592144
e-ISBN	9781467350679
DOI	10.1109/PrimeAsia.2012.6458631
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Resistance Power demand Glitch compensation circuit Power optimization Simulation Layout Logic gates Decoupling capacitors Dynamic IR Drop Transistors Transient analysis Delay
Content Type	Text
Resource Type	Article

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