NDLI: An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects

Content Provider	IEEE Xplore Digital Library
Author	Kar, R. Maheshwari, V. Choudhary, A. Singh, A. Mal, A.K. Bhattacharjee, A.K.
Copyright Year	2010
Description	Author affiliation: Department of Electronics & Communication Engg., National Institute of Technology Durgapur-9, West Bengal, INDIA, 713209 (Kar, R.; Maheshwari, V.; Choudhary, A.; Singh, A.; Mal, A.K.; Bhattacharjee, A.K.)
Abstract	On-chip inductive effects are becoming predominant in deep submicron (DSM) interconnects due to increasing clock speed, circuit complexity and decreasing interconnect lengths. Inductance causes noise in the signal waveforms, which could adversely affect the performance of the circuit and signal integrity. The traditional analysis of crosstalk in a transmission line begins with a lossless LC representation, yielding a wave equation governing the system response. This paper proposes a difference model approach to derive crosstalk in the transform domain. A closed form solution for crosstalk is obtained by incorporating initial conditions using difference modal approach for distributed RLCG interconnects. We have derived the crosstalk metric for two parallel lines when both are switching simultaneously. A raw evaluation of the crosstalk could be at the origin of a malfunction of the circuit. Cross talk can be analyzed by computing the signal linkage between aggressor or attacker nets and victim nets. The attacker net carries a signal that couples to the victim net through the mutual inductance. In order to determine the effects that this cross talk will have on circuit operation, the resulting voltage expressions at the victim and aggressor must be calculated. This paper proposes a difference model approach for the effective voltages at the victim and aggressor using superposition theorem. The accuracy of our approach is justified by the results obtained from SPICE simulation.
Starting Page	362
Ending Page	367
File Size	224579
Page Count	6
File Format	PDF
ISBN	9781424485956
e-ISBN	9781424485949
DOI	10.1109/ICSIP.2010.5697499
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Distributed RLCG line VLSI Crosstalk Integrated circuit interconnections On-Chip Interconnect Equations Couplings Inductance Power transmission lines Difference Model Capacitance Inductive coupling Superposition theorem
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A novel bandwidth estimation method for distributed on-chip RLCG interconnects

Inductive coupling aware explicit cross-talk and delay formula for on-chip VLSI RLCG interconnects using difference model approach

Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects

Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach

Accurate crosstalk analysis for RLCG on-chip VLSI global interconnect

Transfer functions of on-chip global interconnects based on distributed RLCG interconnects model

Coupling aware power estimation for on-chip VLSI distributed RLCG global interconnects using model order reduction technique

A Qualitative Approach to Optimize Coupling Capacitance for Simultaneously Switching Scenario in Coupled VLSI Interconnects

Delay model for VLSI RLCG global interconnects line

An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects

Similar Documents

A novel bandwidth estimation method for distributed on-chip RLCG interconnects

Inductive coupling aware explicit cross-talk and delay formula for on-chip VLSI RLCG interconnects using difference model approach

Bandwidth Modelling for Distributed On-Chip RLCG Interconnect Considering Coupling Effects

Crosstalk aware bandwidth modeling for distributed on-chip RLCG interconnects using difference model approach

Accurate crosstalk analysis for RLCG on-chip VLSI global interconnect

Transfer functions of on-chip global interconnects based on distributed RLCG interconnects model

Coupling aware power estimation for on-chip VLSI distributed RLCG global interconnects using model order reduction technique

A Qualitative Approach to Optimize Coupling Capacitance for Simultaneously Switching Scenario in Coupled VLSI Interconnects

Delay model for VLSI RLCG global interconnects line

An accurate crosstalk noise estimation method for two simultaneously switched on-chip VLSI distributed RLCG global interconnects