NDLI: Unified delay analysis for on-chip RLCG interconnects for ramp input using fourth order transfer function

Content Provider	IEEE Xplore Digital Library
Author	Sengupta, D. Maheshwari, V. Kar, R.
Copyright Year	2010
Description	Author affiliation: Department of Electronics and Communication Engg., National Institute of Technology Durgapur-9, West Bengal, INDIA, 713209 (Sengupta, D.; Maheshwari, V.; Kar, R.)
Abstract	Earlier only the delay caused due to the presence of gates was considered to be an important issue, but now with decreasing feature size and increasing complexity, on-chip interconnect delay has acquired prominence for incremental performance-driven layout synthesis. In this paper, we have obtained an analytical delay model, for RLCG interconnect lines, that in addition to preserving the effectiveness of the previous RLC interconnect models, improves the accuracy for deep submicron technologies that are used at higher frequencies. As the existing works till date, have mostly focused on RC and RLC interconnects with step signal as its input, this approach towards RLCG interconnects is a challenge in itself. In this paper, we have put forward an analytical model, which could accurately capture the on-chip interconnect delay. As we move onto higher frequency ranges, of the order of GHz, the effects of shunt conductance can not be ignored, as that provides a measure of the possible leakage. Due to these reasons, we have derived our on-chip interconnect delay metric considering distributed RLCG segments, rather than sticking to the conventional RLC and RC. The experimental results reveal that our model matches very well with the delay calculations, obtained using SPICE, resulting in an error of less than 4%.
Starting Page	357
Ending Page	361
File Size	146939
Page Count	5
File Format	PDF
ISBN	9781424485956
e-ISBN	9781424485949
DOI	10.1109/ICSIP.2010.5697498
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLSI Integrated circuit interconnections Transfer functions Transfer Function On-Chip Interconnect Delay Analytical models Distributed RLCG Segments Delay Calculation SPICE System-on-a-chip Integrated circuit modeling Ramp Input
Content Type	Text
Resource Type	Article

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