NDLI: Design of encoder for ternary logic circuits

Content Provider	IEEE Xplore Digital Library
Author	Saidutt, P.V. Srinivas, V. Phaneendra, P.S. Muthukrishnan, N.M.
Copyright Year	2012
Description	Author affiliation: Department of Electronics & Telematics Engineering, G. Narayanamma Institute of Technology and Science, Hyderabad, India (Muthukrishnan, N.M.) \|\| Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, India (Saidutt, P.V.; Srinivas, V.; Phaneendra, P.S.)
Abstract	Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented. An encoder is proposed in this paper which can be used in ternary arithmetic circuits. A ternary half adder circuit is designed using the proposed encoder. The proposed design and existing designs are synthesized using Synopsys HSPICE and comparison are drawn for circuit parameters like delay, power etc. Simulation results indicate that the proposed encoder based 1-bit half adder design results in 22% delay reduction, 20% power reduction and 39% power delay product reduction when compared to the existing implementation.
Starting Page	85
Ending Page	88
File Size	968714
Page Count	4
File Format	PDF
ISBN	9781467350655
ISSN	21592144
e-ISBN	9781467350679
DOI	10.1109/PrimeAsia.2012.6458632
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Ternary logic Multivalued logic Threshold voltage CNTFETs Decoding Adders Ternary encoder CNFET
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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