NDLI: Transient analysis for on-chip high speed VLSI RLCG global interconnect for unit impulse input

Content Provider	IEEE Xplore Digital Library
Author	Maheshwari, V. Sharma, A. Majumdar, A. Kar, R. Mandal, D.
Copyright Year	2011
Description	Author affiliation: Department of Electronics and Communication Engg., Hindustan College of Science and Technology, Mathura, Farah -281122, India (Maheshwari, V.; Sharma, A.) \|\| Department of Electronics and Communication Engg., National Institute of Technology, Durgapur-9, West Bengal, INDIA (Majumdar, A.; Kar, R.; Mandal, D.)
Abstract	In paper, the time domain waveform is approximated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect model. It can also be used for multiple interconnect systems but higher order systems are ignored to avoid complexity. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze the rise time and settling time for similar analysis. The model evaluates the performance of a system which is expressed in terms of the transient response for the unit impulse input because it is easy to generate and evaluate the delay analytically. The transient response of a system to a unit impulse input depends upon the initial conditions. In this paper, a new interconnect model is presented; the model is based on the time domain analysis with a unit impulse input signal for on-chip high speed RLCG interconnection network. On-chip inductance and conductance are shown to have a profound effect on the high performance IC design methodologies. In the proposed model, it is shown that when the value of the shunt conductance (G) is increased, the time at which the rise time, settling time and steady state condition is reached, is increased. Hence, for high speed circuit one must increase the value of G, so that the steady state condition is reached as soon as possible. It is also shown that with the increase in the value of G, the delay will reduce. The simulation results performed in Cadence SPICE environment justify the efficacy of the proposed model.
Starting Page	347
Ending Page	351
File Size	1244473
Page Count	5
File Format	PDF
ISBN	9781467300995
e-ISBN	9781467301022
DOI	10.1109/SCOReD.2011.6148763
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-19
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Natural Frequency VLSI RLCG Interconnect Integrated circuit interconnections Damping Ratio Delay Analytical models Inductance Power transmission lines Delay Calculation System-on-a-chip Integrated circuit modeling Time Domain Analysis
Content Type	Text
Resource Type	Article

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