NDLI: Rule-Based Inspection of Wafer Surface

Content Provider	IEEE Xplore Digital Library
Author	Shankar, N.G. Zhong, Z.W.
Copyright Year	2003
Description	Author affiliation: Euro Technology Pte Ltd, Tech Place 1, Singapore 569628 (Shankar, N.G.)
Abstract	A template-based vision system for the 100% inspection of wafer die surfaces has been developed. Design goals included a requirement for the detection of flaws as small as 1μm on parts up to 8-inch wafer size. Each die is treated as one part of the whole wafer. One of the good dies is trained and kept as template die for the whole wafer. The die physical location data are generated, before hand, from CAD designs using a wafer map editor (WME). A separate software package called the wafer map editor was developed to generate setup data needed during the runtime of the inspection process. The WME also generates a part defect wafermap. Each unique die pattern in the wafer is defined as an object and these objects are grouped into userdefined categories such as good die pads and defect die pads. The defect wafer map is used during the runtime inspection of die attach to avoid picking of bad die pads.
Sponsorship	Lee Found. IEEE Montreal Sect. Candian Soc. Mechanical Eng
Starting Page	752
Ending Page	755
File Size	274470
Page Count	4
File Format	PDF
ISBN	078037777X
DOI	10.1109/ICCA.2003.1595123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-12
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inspection Surface treatment Runtime Machine vision Design automation Software packages Microassembly Pattern recognition Semiconductor Automation Rule-Based Defect detection Yield enhancement Image processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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