NDLI: MVP: Capture-power reduction with minimum-violations partitioning for delay testing

Content Provider	IEEE Xplore Digital Library
Author	Zhen Chen Chakrabarty, K. Dong Xiang
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering, Duke University, USA (Chakrabarty, K.) \|\| School of Software, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, China (Dong Xiang) \|\| Department of Computer Science and Technology, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, China (Zhen Chen)
Abstract	Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this paper, we propose minimum-violations partitioning (MVP), a scan-cell clustering method that can support multiple capture cycles in delay testing without increasing test-data volume. This method is based on an integer linear programming model and it can cluster the scan flip-flops into balanced parts with minimum capture violations. Based on this approach, hierarchical partitioning is proposed to make the partitioning method routingaware. Experimental results on ISCAS'89 and IWLS'05 benchmark circuits demonstrate the effectiveness of our method.
Starting Page	149
Ending Page	154
File Size	517049
Page Count	6
File Format	PDF
ISBN	9781424481934
ISSN	10923152
e-ISBN	9781424481941
DOI	10.1109/ICCAD.2010.5654124
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Circuit faults Routing Delay Switches Integrated circuit modeling Power demand
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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