NDLI: An algorithm for exploiting modeling error statistics to enable robust analog optimization

Content Provider	IEEE Xplore Digital Library
Author	Singh, A.K. Lok, M. Ragab, K. Caramanis, C. Orshansky, M.
Copyright Year	2010
Description	Author affiliation: Department of Electrical and Computer Engineering University of Texas at Austin (Singh, A.K.; Lok, M.; Ragab, K.; Caramanis, C.; Orshansky, M.)
Abstract	Equation-based optimization using geometric programming (GP) for automated synthesis of analog circuits has recently gained broader adoption. A major outstanding challenge is the inaccuracy resulting from fitting the complex behavior of scaled transistors to posynomial functions. Fitting over a large region can be grossly inaccurate, and in fact, poor posynomial fit can lead to failure to find a true feasible solution. On the other hand, fitting over smaller regions and then selecting the best region, incurs exponential complexity. In this paper, we advance a novel optimization strategy that circumvents these dueling problems in the following manner: by explicitly handling the error of the model in the course of optimization, we find a potentially suboptimal, but feasible solution. This solution subsequently guides a range-refinement process of our transistor models, allowing us to reduce the range of operating conditions and dimensions, and hence obtain far more accurate GP models. The key contribution is in using the available oracle (SPICE simulations) to identify solutions that are feasible with respect to the accurate behavior rather than the fitted model. The key innovation is the explicit link between the fitting error statistics and the rate of the error uncertainty set increase, which we use in a robust optimization formulation to find feasible solutions. We demonstrate the effectiveness of our algorithm on a two benchmarks: a two-stage CMOS operational amplifier and a voltage controlled oscillator designed in TSMC 0.18µm CMOS technology. Our algorithm is able to identify superior solution points producing uniformly better power and area values under gain constraint with improvements of up to 50% in power and 10% in area for the amplifier design. We also demonstrate that when utilizing the models with the same level of modeling error, our method yields solutions that meet the constraints while the violations for the standard method were as high as 45% and larger than 15% for several constraints.
Starting Page	62
Ending Page	69
File Size	898854
Page Count	8
File Format	PDF
ISBN	9781424481934
ISSN	10923152
e-ISBN	9781424481941
DOI	10.1109/ICCAD.2010.5654325
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Optimization Robustness Uncertainty Transistors SPICE Mathematical model Integrated circuit modeling
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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