NDLI: Local clock skew minimization using blockage-aware mixed tree-mesh clock network

Content Provider	IEEE Xplore Digital Library
Author	Linfu Xiao Zigang Xiao Zaichen Qian Yan Jiang Tao Huang Haitong Tian Young, E.F.Y.
Copyright Year	2010
Description	Author affiliation: Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong (Linfu Xiao; Zigang Xiao; Zaichen Qian; Yan Jiang; Tao Huang; Haitong Tian; Young, E.F.Y.)
Abstract	Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthesis. Local clock skew (LCS) is the clock skew between any two sinks with distance less than or equal to a given threshold. It is defined in the ISPD 2010 High Performance Clock Network Synthesis Contest [1], and it is a novel criterion that captures process variation effects on a clock network. In this paper, we propose a hybrid method that creates a mesh upon a tree topology. Total wire and buffer capacitance is minimized under the LCS and slew constraints. In our method, a clock mesh will be built first according to the positions and capacitance of the sinks. A top-level tree is then built to drive the mesh. A blockage-aware routing method is used during the tree construction. Experimental results show our efficiency and the solution generated by our approach can satisfy the LCS constraint of all the benchmarks in the contest [1], with a fair capacitance usage.
Starting Page	458
Ending Page	462
File Size	1532254
Page Count	5
File Format	PDF
ISBN	9781424481934
ISSN	10923152
e-ISBN	9781424481941
DOI	10.1109/ICCAD.2010.5653732
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-11-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Capacitance Merging Wire Delay Routing Design automation
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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