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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Szu-Yu Chen Yao-Wen Chang |
| Copyright Year | 2010 |
| Description | Author affiliation: Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan Univeristy, Taipei 106, Taiwan (Yao-Wen Chang) || Graduate Institute of Electronics Engineering, National Taiwan Univeristy, Taipei 106, Taiwan (Szu-Yu Chen) |
| Abstract | The double patterning technology (DPT), in which a dense layout pattern is decomposed into two separate masks to relax its pitch, is the most popular lithography solution for the sub-22nm node to enhance pattern printability. Previous works focus on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NC's) which cannot be resolved by any kind of stitch insertion. A design with NC's is not DPT-compliance and will eventually fail the decomposition, resulting in DFM redesign and longer design cycles. In this paper, we give a sufficient condition for the NC existence and propose a geometry-based method for NC prediction to develop an early stage analyzer for DPT decomposability checking. Then, a wire perturbation algorithm is presented to fix as many NC's in the layout as possible. The algorithm is based on iterative 1D-compaction and can easily be embedded into existing industrial compaction systems. Experimental results show that the proposed algorithm can significantly reduce the number of NC's by an average of 85%, which can effectively increase the decomposition success rate for the next stage. |
| Starting Page | 556 |
| Ending Page | 561 |
| File Size | 967843 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424481934 |
| ISSN | 10923152 |
| e-ISBN | 9781424481941 |
| DOI | 10.1109/ICCAD.2010.5654200 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-11-07 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Wire Layout Compaction Tiles Algorithm design and analysis Prediction algorithms Prediction methods |
| Content Type | Text |
| Resource Type | Article |
| Subject | Computer Graphics and Computer-Aided Design Computer Science Applications Software |
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