NDLI: Thermal Characterization and Optimization in Platform FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Sundararajan, P. Gayasen, A. Vijaykrishnan, N. Tuan, T.
Copyright Year	2006
Abstract	Increasing power densities in field programmable gate arrays (FPGAs) have made them susceptible to thermal problems. The advent of platform FPGAs has further exacerbated the problems by increasing the power density variations on the FPGA fabric. Therefore, we need to characterize the die temperature of platform FPGAs. In this paper, we first estimate the temperature distribution within a Virtex-4 FPGA by feeding the block power numbers in an architecture-level temperature simulator calibrated to reflect a real FPGA package. We analyze the impact of different hard-wired blocks on the temperature profile, and observe that they introduce intra-die variation in temperature of up to 20degC. Next, we evaluate the influence of placement on temperature. Our experiments indicate a decrease in peak temperature by changing the placement of hard blocks, especially the high-speed transceivers. We further propose an iterative placement technique to reduce the peak temperature, and apply it on real designs. Finally, we propose alternate organizations of the hard blocks in the FPGA fabric to reduce temperature
Starting Page	443
Ending Page	447
File Size	6719191
Page Count	5
File Format	PDF
ISBN	1595933891
ISSN	10923152
DOI	10.1109/ICCAD.2006.320154
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Field programmable gate arrays Temperature distribution Fabrics Packaging Transceivers Clocks Thermal management Manufacturing Temperature control Logic thermal Platform FPGAs placement Virtex4 temperature
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Computer Science Applications Software

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