NDLI: Design-specific path delay testing in lookup-table-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Menon, P.R. Weifeng Xu Tessier, R.
Copyright Year	1982
Abstract	Due to the increased use of field-programmable gate arrays (FPGAs) in production circuits with high reliability requirements, the design-specific testing of FPGAs has become an important topic for research. Path delay testing of FPGAs is especially important since path delay faults can render an otherwise fault-free FPGA unusable for a given design layout. This paper presents a new approach for FPGA path delay testing, which partitions target paths into subsets that are tested in the same test configuration. Each path is tested for all combinations of signal inversions along the path length. Each configuration consists of a sequence generator, response analyzer, and circuitry for controlling inversions along tested paths, all of which are formed from FPGA resources not currently under test. Two algorithms are presented for target-path partitioning to determine the number of required test configurations. The test circuitry associated with these methods is also described. The results of applying the methods indicate that our path-delay-testing approach requires seconds per design to cover all paths with delay within 10% of the critical path delay. The approach has been validated using Xilinx Virtex devices.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	867
Ending Page	877
Page Count	11
File Size	259911
File Format	PDF
ISSN	02780070
Volume Number	25
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Field programmable gate arrays Circuit testing Circuit faults Logic testing Clocks Manufacturing Built-in self-test Production Programmable logic arrays testing Design automation field programmable gate arrays programmable logic devices
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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