NDLI: A timing-driven data path layout synthesis with integer programming

Content Provider	IEEE Xplore Digital Library
Author	Kim, J. Kang, S.M.
Copyright Year	1997
Description	Author affiliation: Coordinated Sci. Lab., Illinois Univ., Champaign, IL, USA (Kim, J.; Kang, S.M.)
Abstract	We propose an efficient data path synthesis algorithm which generates bit-sliced layouts. Since data path circuits have special characteristics which are different from those of random logic circuits, the dedicated synthesis system is required for efficient layouts. Our main goal in the data path synthesis is to satisfy the timing constraints of circuits as well as to reduce layout areas. Timing-driven placement and over-the-cell routing techniques are developed to generate data path modules. Also, signal interfaces between bit-slices are carefully considered to further reduce layout areas. Our synthesis techniques take advantage of the common characteristics of datapath structures under timing constraints and applies mixed integer linear programming approach to solve the problem. The superior results from our data path synthesis system are demonstrated through comparison with the layout results with the simulated annealing technique.
Starting Page	716
Ending Page	719
File Size	514949
Page Count	4
File Format	PDF
ISBN	0818682000
ISSN	10636757
DOI	10.1109/ICCAD.1995.480209
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Linear programming Signal synthesis Circuit synthesis Timing Routing Delay estimation Logic circuits Simulated annealing Minimization Delay effects
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Timing-driven Data Path Layout Synthesis with Integer Programming

A timing-driven data path layout synthesis with integer programming

Linear programming for optimum hazard elimination in asynchronous circuits

Enhancing timing-driven FPGA placement for pipelined netlists

Post-layout logic duplication for synthesis of Domino circuits with complex gates

Minimizing the Routing Cost During Logic Extraction

Performance-driven global routing based on simulated evolution

Logic optimization algorithm by linear programming approach

Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits

A timing-driven data path layout synthesis with integer programming

Similar Documents

A Timing-driven Data Path Layout Synthesis with Integer Programming

A timing-driven data path layout synthesis with integer programming

Linear programming for optimum hazard elimination in asynchronous circuits

Enhancing timing-driven FPGA placement for pipelined netlists

Post-layout logic duplication for synthesis of Domino circuits with complex gates

Minimizing the Routing Cost During Logic Extraction

Performance-driven global routing based on simulated evolution

Logic optimization algorithm by linear programming approach

Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits

A timing-driven data path layout synthesis with integer programming