NDLI: Switching activity analysis using Boolean approximation method

Content Provider	IEEE Xplore Digital Library
Author	Uchino, T. Minami, F. Mitsuhashi, T. Goto, N.
Copyright Year	1997
Description	Author affiliation: Toshiba Corp., Kawasaki, Japan (Uchino, T.; Minami, F.; Mitsuhashi, T.)
Abstract	This paper presents a novel algorithm to estimate the signal probability and switching activity at all nodes in a combinational logic circuit under a zero-delay model without constructing global BDDs. By using Taylor expansion technique, the first-order signal correlation effects due to reconvergent fan-out nodes are taken into account. High accuracy is achieved by considering the dependency of the signal probability and switching activity on each primary input. High speed is also achieved by using the incremental approach for probability calculation. Our approach is able to handle large circuits, since it does not need to construct global BDDs for the probability calculation. The analysis of the time complexity and the experimental results show the running time of our approach to be about 100 times shorter than that of the most accurate approach previously proposed and that our approach has comparable accuracy. The error of the total power estimation is about 0.5% on average.
Starting Page	20
Ending Page	25
File Size	547763
Page Count	6
File Format	PDF
ISBN	0818682000
ISSN	10636757
DOI	10.1109/ICCAD.1995.479880
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Approximation methods Probability Magnesium compounds Data structures Boolean functions Switching circuits Taylor series Circuit testing Delay estimation Logic testing
Content Type	Text
Resource Type	Article

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