NDLI: Functional test generation for delay faults in combinational circuits

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I. Reddy, S.M.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA (Pomeranz, I.; Reddy, S.M.)
Abstract	We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. It can also potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of branch and bound strategies. A parameter called /spl Delta/ is used to control the number of functional faults targeted and thus the number of tests generated. If /spl Delta/ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given function. An appropriate subset of tests can be selected once the implementation is known. The test sets generated for various values of /spl Delta/ are fault simulated on gate-level realizations to demonstrate their effectiveness.
Starting Page	687
Ending Page	694
File Size	958908
Page Count	8
File Format	PDF
ISBN	0818682000
ISSN	10636757
DOI	10.1109/ICCAD.1995.480204
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-11-05
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Delay Circuit faults Combinational circuits Robustness Logic testing Cities and towns Costs Electrical fault detection Fault detection
Content Type	Text
Resource Type	Article

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