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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | de Jong, G. Lin, B. Verdonck, C. Wuytack, S. Catthoor, F. |
| Copyright Year | 1997 |
| Description | Author affiliation: IMEC, Leuven, Belgium (de Jong, G.; Lin, B.; Verdonck, C.; Wuytack, S.; Catthoor, F.) |
| Abstract | Telecommunication network management applications often require application-specific ICs that use large dynamically allocated stored data structures. Currently available hardware synthesis environments typically do not support dynamic data structure concepts and their associated memory synthesis problems. In this paper we address the background memory management task in a hardware design trajectory, which includes allocation of a distributed memory architecture, assignment and mapping of abstract data structures to memories, and synthesis of dynamic management behavior. With this approach to explore for the optimal memory architecture, the design entry point is lifted to a higher level than currently used for behavioral synthesis, as the specification can be a high-level program using data abstraction. The power of our approach will be substantiated on an industrial high-performance telecommunication ASIC design. |
| Starting Page | 515 |
| Ending Page | 520 |
| File Size | 701614 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818682000 |
| ISSN | 10636757 |
| DOI | 10.1109/ICCAD.1995.480165 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-11-05 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Memory management Data structures Hardware Network synthesis Memory architecture Signal processing algorithms Runtime Telecommunication network management Partitioning algorithms Tree data structures |
| Content Type | Text |
| Resource Type | Article |
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